Taiwan Semiconductor Manufacturing Co (TSMC, 台積電), the world’s largest foundry service provider, yesterday said that global semiconductor revenue is projected to hit US$1.5 trillion in 2030, after the figure exceeds US$1 trillion this year, as artificial intelligence (AI) demand boosts consumption of token and compute power.
“We are still at the beginning of the AI revolution, but we already see a significant impact across the whole semiconductor ecosystem,” TSMC deputy cochief operating officer Kevin Zhang (張曉強) said at the company’s annual technology symposium in Hsinchu City.
“It is fair to say that in the past decade, smartphones and other mobile devices were the main driver for the growth of semiconductors, but ... AI will be the one to carry us into the next decade or far beyond,” Zhang said.
Photo: Daniel Ceng, AP
In 2030, AI and high-performance computing applications are to contribute about 55 percent of global semiconductor revenue, estimated to be US$1.5 trillion, he said.
That goes against the conventional idea that edge devices consume the most silicon, he said.
By that time, AI inference would greatly outpace AI training and would become the main semiconductor growth driver, data that Zhang shared showed.
This year, AI inference and AI training would each account for half of the growth, the data showed.
Last year, TSMC helped create more than US$350 billion in semiconductor revenue for chip companies, mostly from the US, Zhang said.
That would exceed US$1 trillion in four years, he added.
To address customer demand, TSMC has accelerated capacity expansion at an unprecedented pace for chips and advanced packaging, the company said.
It is ramping up 2-nanometer chip capacity at five factories in Hsinchu and Kaohsiung this year, TSMC vice president for operations and advanced technology engineering B.Z. Tien (田博仁) said.
That would increase the annual compound growth rate of 2-nanometer chip capacity to 70 percent next year and in 2028, Tien said.
TSMC is also aggressively expanding its advanced chip-on-wafer-on-substrate (CoWoS) packaging capacity at an annual compound growth rate of 90 percent from 2022 to next year to meet customer demand for AI chips, the company said.
The third generation of CoWoS technology entered volume production this year, offering a larger interposer with a 5.5-fold reticle size to accommodate 12 high-bandwidth memory (HBM) chips, TSMC vice president for business development Lipen Yuan (袁立本) said.
The company has significantly improved its CoWoS yield rate to 98 percent, Yuan said.
By 2029, TSMC aims to provide CoWoS with a reticle 14 times larger to accommodate 24 HBM chips, he said.
In addition, TSMC is developing new system-on-wafer packaging technology to scale reticle size more than 40-fold to accommodate 64 HBM chips, he added.
This year, TSMC plans to offer its compact universal photonics engine (COUPE) technology, which integrates multiple integrated circuits, photonics and fiber couplers into a single package, it said.
The company plans to integrate COUPE into the CoWoS package, it said.
COUPE technology used in data centers would help reduce coupling loss, boost energy efficiency and accelerate chip-to-chip connectivity, TSMC added.
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