Taiwan Semiconductor Manufacturing Co (TSMC, 台積電) yesterday said its newest A13 chip is to enter volume production in 2029 as the chipmaker seeks to hold onto its tech leadership and demand for next-generation chips used in artificial intelligence (AI), high-performance-computing (HPC) and mobile applications.
TSMC, the world’s biggest contract chipmaker, also unveiled its A12 chip at its annual technology symposium in Santa Clara, California.
The A12 chip, which features TSMC’s super-power-rail technology to provide backside power delivery for AI and HPC applications, is also to enter volume production in 2029, a year after the scheduled release of the A14 chip.
Photo: AP
The technology moves the power rails from the front side, where components are, to the back side of the wafer to ensure more efficient power delivery to transistors. It would be first used in TSMC’s A16 chip, which is set to enter production in the second half of this year.
“At TSMC, we understand our customers are always looking ahead to their next innovation and they come to us for a reliable stream of new silicon technologies, like A13, meticulously engineered to be ready for high-volume production right when their visionary new designs demand them,” TSMC chairman and CEO C.C. Wei (魏哲家) said.
“TSMC’s advanced process technologies lead the industry in density, performance and power efficiency,” he said.
The A13 chip provides 6 percent area savings, and better power efficiency and performance compared with the A14 chip, the chipmaker said.
To support demand for more computing power and memory in a single package, TSMC said it would expand the reticle size on chip-on-wafer-on-substrate (CoWoS) to 14 reticles in 2028 and to more than 14 the next year, compared with the 5.5-reticle CoWoS it currently produces.
A 14-reticle CoWoS is capable of integrating approximately 10 large compute chips and 20 high-bandwidth-memory stacks, it said.
The new offerings provide customers with more options for AI compute scaling and complement TSMC’s 40-reticle system-on-wafer-X technology, also expected in 2029, it added.
TSMC is to offer its 3D chip stacking technology, called system on an integrated chip, on its most advanced platform, with A14-to-A14 system on an integrated chip set to be available for production in 2029, it said.
The chipmaker also said it plans to begin production of its first co-packaged optics solution using its compact universal photonic engine on substrate this year.
By integrating the compact universal photonic engine on substrate directly inside the package, TSMC is able to double the power efficiency and 10 times the latency reduction versus a pluggable version on a circuit board.
The technology is featured in a 200 gigabits per second microring modulator, a highly compact and energy-efficient solution to move data between racks in data centers, TSMC said.
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